The present invention concerns the fabrication of a capacitor for use in very large scale integrated (VLSI) circuits.
Various capacitor structures have been investigated for use in VLSI circuits. For example, see the various capacitor structures suggested by C. Kaya, H. Tigelaar, J. Paterson, M. de Wit, J. Fattaruso, D. Hester, S. Kiriakai, K. Tan, F. Tsay, Polycide/Metal Capacitors for High Precision A/D Converters, IEDM, 1988, pp. 782-785.
The voltage linearity of a capacitor is the change in normalized capacitance of the capacitor per unit change in the voltage across the capacitor. A smaller linearity implies a more stable capacitance, which is desirable. In poly-to-poly capacitors, increasing doping concentration of the polysilicon electrodes of a capacitor reduces the voltage linearity of the capacitor. However, as the circuit density of VLSI circuits increases, high doping of polysilicon can result in an increased potential for a leakage current through the oxide. See, for example, T. Ono, T. Mori, T. Ajioka, T. Takayashiki, Studies of Thin Poly Si Oxides for E and E.sup.2 PROM, IEDM, 1985, pp. 380-383, and T. Iida, M. Nakahara, S. Gotoh and H. Akiba, Precise Capacitor Structure Suitable for Submicron Mixed Analog/Digital ASICs, Custom Integrated Circuits Conference, 1990, pp. 18.5.1-18.5.4. Additionally, the fabrication of poly-to-poly capacitors generally requires high temperature doping and oxidation steps, which can adversely affect reliability and performance of the integrated circuit components. Also, the metal-to-poly capacitor and the metal-to-polycide require additional processing steps which add to the complexity of the circuit and in many cases adversely affect reliability, or compromise performance. For poly-to-poly capacitors in which the top electrode is polycide, the capacitor has poor characteristics which require additional processing. The additional processing can be cost prohibitive.